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d a t a sh eet product speci?cation supersedes data of september 1993 file under integrated circuits, ic06 1998 jun 04 integrated circuits 74hc/hct595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
1998 jun 04 2 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 features 8-bit serial input 8-bit serial or parallel output storage register with 3-state outputs shift register with direct clear 100 mhz (typ) shift out frequency output capability: C parallel outputs; bus driver C serial output; standard i cc category: msi. applications serial-to-parallel data conversion remote control holding register. description the 74hc/hct595 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 595 is an 8-stage serial shift register with a storage register and 3-state outputs. the shift register and storage register have separate clocks. data is shifted on the positive-going transitions of the sh cp input. the data in each register is transferred to the storage register on a positive-going transition of the st cp input. if both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. the shift register has a serial input (d s ) and a serial standard output (q 7 ) for cascading. it is also provided with asynchronous reset (active low) for all 8 shift register stages. the storage register has 8 parallel 3-state bus driver outputs. data in the storage register appears at the output whenever the output enable input (oe) is low. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc ; for hct the condition is v i = gnd to v cc - 1.5 v. symbol parameter conditions typ. unit hc hct t phl /t plh propagation delay c l = 15 pf; v cc =5v sh cp to q 7 1621ns st cp to q n 17 20 ns mr to q 7 1419ns f max maximum clock frequency sh cp , st cp 100 57 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 115 130 pf
1998 jun 04 3 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 ordering information pinning type number package name description version 74hc595n dip16 plastic dual in-line package; 16 leads (300 mil); long body sot38-1 74HC595D so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74HC595Db ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74hc595pw tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74hct595n dip16 plastic dual in-line package; 16 leads (300 mil); long body sot38-1 74hct595d so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 symbol pin description q 0 to q 7 15, 1 to 7 parallel data output gnd 8 ground (0 v) q 7 9 serial data output mr 10 master reset (active low) sh cp 11 shift register clock input st cp 12 storage register clock input oe 13 output enable (active low) d s 14 serial data input v cc 16 positive supply voltage fig.1 pin configuration. handbook, halfpage q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' q 0 d s gnd st cp sh cp v cc oe 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 595 mla001 mr fig.2 logic symbol. handbook, halfpage oe mr 9 15 1 2 3 4 5 6 7 13 10 14 11 12 mla002 q 1 q 0 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' d s st cp sh cp
1998 jun 04 4 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 fig.3 iec logic symbol. handbook, halfpage msa698 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 en3 srg8 r 3 oe mr q 1 q 0 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' d s st cp sh cp fig.4 functional diagram. handbook, full pagewidth st cp d s sh cp mr q 7 ' 8-stage shift register 8-bit storage register 14 11 10 12 9 oe 3-state outputs q 1 q 2 q 3 q 5 q 6 q 7 q 4 q 0 15 1 2 3 4 5 6 7 13 mla003
1998 jun 04 5 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 fig.5 logic diagram. handbook, full pagewidth stage 0 stages 1 to 6 stage 7 ff0 d cp q r latch d cp q ff7 d cp q r latch d cp q mla010 dq q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' q 0 d s st cp sh cp oe mr
1998 jun 04 6 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 function table notes 1. h = high voltage level; l = low voltage level - = low-to-high transition; = high-to-low transition z = high-impedance off-state; nc = no change x = dont care. inputs outputs functon sh cp st cp oe mr d s q 7 q n x x l l x l nc a low level on mr only affects the shift registers x - l l x l l empty shift register loaded into storage register x x h l x l z shift register clear. parallel outputs in high-impedance off-state - xlhhq 6 nc logic high level shifted into shift register stage 0. contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal q 6 ) appears on the serial output (q 7 ) x - lhxncq n contents of shift register stages (internal q n ) are transferred to the storage register and parallel output stages -- lhxq 6 q n contents of shift register shifted through. previous contents of the shift register is transferred to the storage register and the parallel output stages.
1998 jun 04 7 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 fig.6 timing diagram. handbook, full pagewidth high-impedance off-state st cp d s sh cp mr oe q 1 q 0 q 7 ' q 6 q 7 mla005 - 1
1998 jun 04 8 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 dc characteristics for 74hc for the dc characteristics see chapter 74hc/hct/hcu/hcmos logic family specifications . output capability: parallel outputs, bus driver, serial output, standard i cc category: msi. ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max t phl /t plh propagation delay sh cp to q 7 - 52 160 - 200 - 240 ns 2.0 fig.7 - 19 32 - 40 - 48 4.5 - 15 27 - 34 - 41 6.0 t phl /t plh propagation delay st cp to q n - 55 175 - 220 - 265 ns 2.0 fig.8 - 20 35 - 44 - 53 4.5 - 16 30 - 37 - 45 6.0 t phl propagation delay mr to q 7 - 47 175 - 220 - 265 ns 2.0 fig.10 - 17 35 - 44 - 53 4.5 - 14 30 - 37 - 45 6.0 t pzh /t pzl 3-state output enable time oe to q n - 47 150 - 190 - 225 ns 2.0 fig.11 - 17 30 - 38 - 45 4.5 - 14 26 - 33 - 38 6.0 t phz /t plz 3-state output disable time oe to q n - 41 150 - 190 - 225 ns 2.0 fig.11 - 15 30 - 38 - 45 4.5 - 12 26 - 33 - 38 6.0 t w shift clock pulse width high or low 75 17 - 95 - 110 - ns 2.0 fig.7 15 6 - 19 - 22 - 4.5 13 5 - 16 - 19 - 6.0 t w storage clock pulse width high or low 75 11 - 95 - 110 - ns 2.0 fig.8 15 4 - 19 - 22 - 4.5 13 3 - 16 - 19 - 6.0 t w master reset pulse width low 75 17 - 95 - 110 - ns 2.0 fig.10 15 6.0 - 19 - 22 - 4.5 13 5.0 - 16 - 19 - 6.0 t su set-up time d s to sh cp 50 11 - 65 - 75 - ns 2.0 fig.9 10 4.0 - 13 - 15 - 4.5 9.0 3.0 - 11 - 13 - 6.0 t su set-up time sh cp to st cp 75 22 - 95 - 110 - ns 2.0 fig.8 15 8 - 19 - 22 - 4.5 13 7 - 16 - 19 - 6.0
1998 jun 04 9 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 t h hold time d s to sh cp 3 - 6 - 3 - 3 - ns 2.0 fig.9 3 - 2 - 3 - 3 - 4.5 3 - 2 - 3 - 3 - 6.0 t rem removal time mr to sh cp 50 - 19 - 65 - 75 - ns 2.0 fig.10 10 - 7 - 13 - 15 - 4.5 9 - 6 - 11 - 13 - 6.0 f max maximum clock pulse frequency sh cp or st cp 930 - 4.8 - 4 - mhz 2.0 figs 7 and 8 30 91 - 24 - 20 - 4.5 35 108 - 28 - 24 - 6.0 symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max
1998 jun 04 10 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 dc characteristics for 74hct for the dc characteristics see chapter 74hc/hct/hcu/hcmos logic family specifications . output capability: parallel outputs, bus driver; serial output, standard i cc category: msi. note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. gnd = 0 v; t r =t f = 6 ns; c l =50pf. input unit load coefficient d s 0.25 mr 1.50 sh cp 1.50 st cp 1.50 oe 1.50
1998 jun 04 11 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max t phl / t plh propagation delay sh cp to q 7 - 25 42 - 53 - 63 ns 4.5 fig.7 t phl / t plh propagation delay st cp to q n - 24 40 - 50 - 60 ns 4.5 fig.8 t phl propagation delay mr to q 7 - 23 40 - 50 - 60 ns 4.5 fig.10 t pzh / t pzl 3-state output enable time oe to q n - 21 35 - 44 - 53 ns 4.5 fig.11 t phz / t plz 3-state output disable time oe to q n - 18 30 - 38 - 45 ns 4.5 fig.11 t w shift clock pulse width high or low 16 6 - 20 - 24 - ns 4.5 fig.7 t w storage clock pulse width high or low 16 5 - 20 - 24 - ns 4.5 fig.8 t w master reset pulse width low 20 8 - 25 - 30 - ns 4.5 fig.10 t su set-up time d s to sh sp 16 5 - 20 - 24 - ns 4.5 fig.9 t su set-up time sh cp to st cp 16 8 - 20 - 24 - ns 4.5 fig.8 t h hold time d s to sh cp 3 - 2 - 3 - 3 - ns 4.5 fig.9 t rem removal time mr to sh cp 10 - 7 - 13 - 15 - ns 4.5 fig.10 f max maximum clock pulse frequency sh cp or st cp 30 52 - 24 - 20 - mhz 4.5 figs 7 and 8
1998 jun 04 12 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 ac waveforms fig.7 waveforms showing the clock (sh cp ) to output (q 7 ) propagation delays, the shift clock pulse width and maximum shift clock frequency. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth msa699 t plh t phl t w 1/f max v m (1) v m (1) sh cp input q 7 ' output t thl t tlh 90% 10% fig.8 waveforms showing the storage clock (st cp ) to output (q n ) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth msa700 t plh t phl t w 1/f max v m (1) v m (1) v m (1) st cp input t su sh cp input q n output
1998 jun 04 13 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 fig.9 waveforms showing the data set-up and hold times for the d s input. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth mlb196 t h t su t h t su q 7 ' output sh cp input d s input v m (1) v m (1) v m (1) fig.10 waveforms showing the master reset ( mr) pulse width, the master reset to output (q 7 ) propagation delay and the master reset to shift clock (sh cp ) removal time. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth mlb197 t phl t w v m (1) v m (1) v m (1) sh cp input t rem mr input q 7 ' output
1998 jun 04 14 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 fig.11 waveforms showing the 3-state enable and disable times for input oe. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth msa697 t plz t phz outputs disabled outputs enabled 90% 10% outputs enabled oe input v m (1) t pzl t pzh v m (1) v m (1) q n output low-to-off off-to-low q n output high-to-off off-to-high t r t f 90% 10%
1998 jun 04 15 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 package outlines unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 92-10-02 95-01-19 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.10 0.020 0.19 050g09 mo-001ae m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
1998 jun 04 16 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1998 jun 04 17 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot338-1 94-01-14 95-02-04 (1) w m b p d h e e z e c v m a x a y 1 8 16 9 q a a 1 a 2 l p q detail x l (a ) 3 mo-150ac pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 a max. 2.0
1998 jun 04 18 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1.0 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 94-07-12 95-04-04 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.10 pin 1 index
1998 jun 04 19 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so, ssop and tssop r eflow soldering reflow soldering techniques are suitable for all so, ssop and tssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering can be used for all so packages. wave soldering is not recommended for ssop and tssop packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering is used - and cannot be avoided for ssop and tssop packages - the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end.
1998 jun 04 20 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74hc/hct595 even with these conditions: only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1). do not consider wave soldering tssop packages with 48 leads or more, that is tssop48 (sot362-1) and tssop56 (sot364-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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